As is known in the art, many present Microwave (Millimeter-wave) Monolithic Integrated Circuit (MMIC) fabrication processes require two deposited layers of Plasma Enhanced Chemical Vapor Deposition (PECVD) silicon nitride (SiN): (1) thin (<100-nm) layer for surface passivation (Pass-SiN) of the transistors; and (2) a thick (>200-nm) layer for robust Metal-Insulator-Metal (MIM) capacitors (Cap-SiN). These two layers are over the active region between the source and drain contacts of the transistors. In this scenario, the latter layer or film is not essential on the transistor yet it adds unwanted parasitic capacitances between the metal contacts in the active region (e.g. source-gate, gate-drain, and source-drain) that deleteriously load the radio frequency (rf) gain performance of the device. This becomes a significant problem for millimeter-wave devices where gain becomes the limiting component to its overall performance.
This RF loading by the Cap-SiN is best exemplified on gallium nitride (GaN) based high electron mobility transistors (HEMTs), where the gain (GMAX) across frequency may be lowered by up to 2.0-2.5 dB when the 200-nm Cap-SiN is added. Since the function of this film does not bring any benefit to the HEMT, the finished device inherently incurs this 2-3 dB gain reduction. Therefore, there is a need to decouple the Cap-SiN from the Pass-SiN in the transistor.
Pass-SiN films and similar ones from other groups has proven over the years to be an essential feature of the device because of its ability to dramatically reduce rf dispersion effects to tolerant levels that otherwise would be significantly deleterious to overall device power performance.
The common method to realize Pass- and Cap-SiN for MMICs is by deposition at approximately 300 C with PECVD. For the latter film, this elevated temperature process eliminates the ability for selective area deposition with standard photolithography processes. Thus this film must be blanket-coated over the whole wafer and then selectively patterned to form MIM capacitors. However, because the deposition conditions for both SiN films are the same, selectively removing upper portions of the Cap-SiN layer in a reproducible manner down to the Pass-SiN to thin the dielectric for the transistor relative to the thickness desired for the capacitor SiN layer is extremely difficult and impractical on a production level.
Another issue is that the PECVD Pass-SiN layer is deposited on the semiconductor after the semiconductor has been removed from the growth apparatus causing significant surface contamination from air exposure. High concentrations of contaminants such as carbon, oxygen, and silicon are now present on the air-exposed surface, which are very difficult to remove prior to PECVD deposition. Residual contaminants, which become buried at the semiconductor/Pass-SiN interface, are in the high electric field region between the gate and drain electrodes of the transistor, which can lead to deleterious transistor leakage currents.